1. Field of the Invention
The invention relates generally to photo sensors. More particularly, the invention relates to numerical full well capacity extension for photo sensors with an integration capacitor in the readout circuit using two and four phase charge subtraction.
2. Description of Related Art
Ideally, an electronic photo detection system should translate the incoming photon signal into an electronic signal with maximum fidelity, for example, without adding noise, signal distortion or saturation towards high intensities. This ideal situation can only be approximated by any real detection system, and in practice most systems are restricted to specific lighting and/or operating conditions to satisfy this requirement over a limited range. The wider this operating range, the more powerful the sensor system and the less the restrictions that have to be applied to the operating conditions.
Recent advances in photo detection systems focus on digitizing the photon signal at the integration node itself. One prior art approach injects a known amount of charge of opposite polarity into the readout node, as soon as the output signal is getting close to the saturation limit. FIG. 1 illustrates the circuit diagram for this negative charge injection. Charge may be subtracted and the dynamic range may be extended by keeping track of the number of negative charge injections without reducing system sensitivity.
This prior art approach has several disadvantages. First, it can only be applied if the readout node has low impedance, for example, (Capacitor or) Charge Trans-Impedance Amplifier (CTIA) type readout. The approach is not suited for Direct Injection (DI), Buffered Direct Injection (BDI) or floating diffusion type front end circuits with a high impedance integration node. Second, an additional capacitor has to be connected to the input node, which increases the size and noise of the front end circuit. Finally, it requires twice as many charge removal cycles compared to the rotating capacitor approach of this invention, assuming the same total capacitance per unit cell and the same full well capacity.
Another approach, illustrated in FIG. 2, uses a current sink that controls the current flow in the circuit while maintaining low noise characteristics. However, one disadvantage of using the current sink is that it requires a large unit cell in order to achieve low noise performance. Since technology is moving towards smaller photo detection systems, this prior art approach is less favorable.
Full well capacity is the total amount of charge that a conventional image can handle without saturation. The charge on a capacitor may be determined by multiplying the voltage across the capacitor times the capacitor value. A CTIA may be used for infrared and other sensing applications. The CTIA integrates the current generated from a detector over a period of time to provide a measurable output voltage signal. Conventional CTIAs provide high sensitivity amplification of signals from infrared detectors, independent of the detector capacitance.
In photo detection applications with very high backgrounds and/or high signal levels such as long wave infrared imagers, the physically achievable full well capacity of one individual pixel of an imaging array is typically too small to integrate all charge carriers that are generated per 1 frame time. As a result, the integration time for conventional applications is reduced below the frame time in order to avoid saturation.
Numerous prior art methods focus on maximizing the size of the integration capacitor and/or the output voltage swing. However, practical limitations of pixel size, achievable specific capacitance per area and maximum voltage, tolerated by the integrated circuit process, nevertheless make it impossible to capture all of the physically available information with these techniques that scale poorly with process generations. Also, a larger integration capacitor corresponds to lower sensitivity in terms of output voltage swing per photo generated charge carrier. This would reduce the dynamic range towards the low intensity region. As such, the number of detector sites is limited, as is the minimum spacing between detector sites, thereby limiting the achievable image resolution.
In shot noise dominated applications, this limited full well capacity defines the achievable Noise Equivalent Delta Temperature (NEDT). If only a part of the generated signal charge can be integrated, a part of the physically available information would be lost in the detection process.
With an increasing demand for improved detectors, there remains a need in the art for a charge removal process in the readout circuit using numerical full well capacity extension that provides higher full well capacity without sacrificing the size of the unit cell in the imaging array or lowering the light level sensitivity.